
Si8450/51/52/55
Table 3. Electrical Characteristics (Continued)
(V DD1 = 5 V±10%, V DD2 = 5 V±10%, T A = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V DD1
V DD2
—
—
4.3
4.8
6.5
6.7
mA
Si8451Bx
V DD1
V DD2
—
—
4.4
5.0
6.2
7.0
mA
Si8452Bx
V DD1
V DD2
—
—
4.6
4.8
6.4
6.7
mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V DD1
V DD2
—
—
4.6
24
6.9
30
mA
Si8451Bx
V DD1
V DD2
—
—
8.6
20.4
10.8
25.5
mA
Si8452Bx
V DD1
V DD2
—
—
12.6
16.5
15.8
20.6
mA
Timing Characteristics
Si845xAx
Maximum Data Rate
Minimum Pulse Width
0
—
—
—
1.0
250
Mbps
ns
Propagation Delay
Pulse Width Distortion
t PHL , t PLH
PWD
See Figure 2
See Figure 2
—
—
—
—
35
25
ns
ns
|t PLH - t PHL |
Propagation Delay Skew 2
Channel-Channel Skew
t PSK(P-P)
t PSK
—
—
—
—
40
35
ns
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 ? , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t PSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 26 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.5